Generally, devices such as a thyristor, a DMOS transistor (Double-diffusion MOS transistor), or a bipolar transistor are used as a high-voltage ESD protection device. An SCR (Silicon Controlled Rectifier) device, one typical example of the thyristor device, is composed of an anode and a cathode, and charges in the SCR device can move in a lateral direction.
FIG. 1 is a cross sectional view illustrating a conventional ESD protection SCR device.
Referring to FIG. 1, a conventional ESD protection SCR device includes an n-type deep well 15, a first well 20 and a second well 25. The n-type deep well 15 is formed on an upper surface of a p-type semiconductor substrate 10. N-type impurities are implanted into a left portion of the n-type deep well 20 to form the first well 15, whereas p-type impurities are implanted into a right portion of the n-type deep well 15 to form the second well 25. A region in which the first well 20 is formed corresponds to an anode region, whereas a region in which the second well 25 is formed corresponds to a cathode region.
Further, n-type and p-type impurities are implanted into the first well 20 to form an n-type impurity region 30 and a p-type impurity region 35, respectively, which are both connected to an anode terminal. On the other hand, p-type and n-type impurities are implanted into the second well 25 to form a p-type impurity region 40 and an n-type impurity region 45, respectively, which are both connected to a cathode terminal.
N-type impurities are implanted into one side of the p-type impurity region 35 in the first well 20 to form an n-type impurity region 50 floating without being connected to the anode terminal, whereas p-type impurities implanted into one side of the n-type impurity region 45 in the second well 25 to form an p-type impurity region 55 floating without being connected to the cathode terminal.
A device isolation layer 60 is provided to separate the impurity regions 30, 35, 40, 45, 50, and 55 from each other. The ESD protection SCR device 1 is formed in a bilaterally symmetrical structure with respect to the p-type impurity region 40. In order to use the ESD protection SCR device 1 as an electrostatic discharge protection device, the anode terminal is connected to a VDD terminal, and the cathode terminal is connected to a ground terminal.
The ESD protection SCR device 1 can be utilized for protecting a semiconductor device from static electricity, and when the electrostatic voltage is applied at high levels such as 2 kV or more, the SCR device 1 can rapidly drain out the electrostatic current to the ground terminal. Therefore, in order for the ESD protection SCR device 1 to function as an electrostatic discharge protection device, both a first trigger voltage at which the ESD protection SCR device 1 operates, and a second trigger voltage at which the ESD protection SCR device 1 breaks down due to heat generation must be lower than a breakdown voltage of internal circuits that make up the device 1, and the holding voltage which corresponds to a lowered voltage after the ESR protection SCR device 1 is triggered, should be lower than an operating voltage of the internal circuits.
Typically, the ESD-protection SCR device has relatively a low holding voltage due to its structural characteristics, which can lead to undesired latch-up problems due to over-voltage and noise other than ESD under normal operating conditions. The ESD protection SCR device 1 shown in FIG. 1 has the holding voltage higher than that of the typical ESD protection SCR device, but still has a limitation in securing a holding voltage of over 30 V or more and a high voltage resistance. Further, when the ESD protection SCR device 1 is implemented to an actual chip, a trigger voltage or a holding voltage along a parasitic path due to an interaction with adjacent components is lower than the trigger voltage or the holding voltage of the ESD protection SCR device 1, which may cause a problem that an operation of the ESD protection SCR device 1 is distorted.